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?2010 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN4800AS/CS/01S/02S " Rev. 1.0.2
16
 
PWM Control (RAMP)
When the PWM section is used in current mode, RAMP
is generally used as the sampling point for a voltage,
representing the current in the primary of the PWMs
output transformer. The voltage is derived either from a
current-sensing resistor or a current transformer. In
voltage mode, RAMP is the input for a ramp voltage
generated by a second set of timing components (R
RAMP
,
C
RAMP
) that have a minimum value of 0V and a peak
value    of    approximately    6 V.    In    voltage    mode,
feedforward from the PFC output bus is an excellent
way to derive the timing ramp for the PWM stage.
Generating V
DD
 
After turning on the FAN4800AS/CS/01S/02S at 11 V,
the operating voltage can vary from 9.3 V to 28 V. The
threshold voltage of the V
DD
  OVP comparator is 28 V
and its hysteresis is 1 V. When V
DD
  reaches 28 V,
OPFC is LOW and the PWM section is not disturbed.
There are two ways to generate V
DD
: use auxiliary
power supply around 15 V or use bootstrap winding to
self-bias   the   FAN4800AS/CS/01S/02S   system.   The
bootstrap winding can be taped from the PFC boost
choke or the transformer of the DC-to-DC stage.
Leading/Trailing Edge Modulation
Conventional PWM techniques employ trailing-edge
modulation, in which the switch turns on right after the
trailing edge of the system clock. The error amplifier
output is then compared with the modulating ramp up.
The effective duty cycle of the trailing-edge modulation
is determined during the on-time of the switch.
In the case of leading-edge modulation, the switch is
turned off exactly at the leading edge of the system
clock. When the modulating ramp reaches the level of
the error amplifier output voltage, the switch is turned
on.   The   effective   duty-cycle   of   the   leading-edge
modulation is determined during off-time of the switch.
 
 
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